| 摘要: |
| 设备端的通信产品要求启动快，采用FPGA芯片时，加载时间要小于2秒，针对这个要求，介绍了企业中最常用的FPGA从串加载方案，提出了一种利用CPLD提高FPGA加载速度的方案，并就改进方案给出数据分析结果。该方案理论计算结果表明：当CPLD工作时钟33MHZ时，加载Altera公司的EP3C120 FPGA，加载所需时间1.65s。CPLD工作时钟提高，加载时间会大幅缩短，完全满足通信产品的要求，且该方案便于移植，可以应用于任何型号的FPGA加载。 |
| 关键词: FPGA加载速度 CPLD 从串加载 工作时钟 占用资源 启动 DDR2 |
| DOI： |
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| 基金项目:2012年浙江机电职业技术学院科技孵化课题基金资助项目 |
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| Using CPLD improve FPGA loading speed |
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| Abstract: |
| Device-side communication products must boot very quickly, the FPGA chip loading time should be less than two seconds, according to this requirement, Describing the most commonly used FPGA loading program, slave serial solution. Provide a solution of using CPLD to configure FPGA, and data analysis is given on the improvement program. The calculation results show that loading time of EP3C120 is 1.65 seconds, when the CPLD clock is 33MHZ.If the CPLD clock frequency is promoted, FPGA loading time is greatly shortened, fully meet the communication products, and the scheme is easy to transplant, can be applied to any type of FPGA loading. |
| Key words: FPGA loading speed CPLD salve serial working clock occupied resources Boot DDR2 |