| 摘要: |
| 数字中频系统中高速ADC、DAC对采样时钟有着很高的要求，对此设计了一种新的基于AD9516的CDMA2000数字中频系统采样时钟合成方案。本文在提出该数字中频系统硬件方案的基础上，介绍了AD9516芯片及其在本系统中的具体应用，给出了MCU与AD9516数据通信方式和芯片主要寄存器配置内容，且详细分析了时钟相位噪声和时钟抖动的测试方法。最终在对基于此时钟方案制作出来的数字中频系统PCB板仔细调试之后，测试了时钟相噪与抖动以及整个系统SNR,整体指标达到设计要求。 |
| 关键词: 数字中频 AD9516 相位噪声 时钟抖动 SNR |
| DOI： |
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| Design and apply of broadband high-dynamic digital intermediate frequency system sampling clock based on AD9516 |
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| Abstract: |
| High-speed ADC、DAC in digital intermediate frequency system has a high requirement to sampling clock , a new sampling clock synthesis method which based on AD9516 for CDMA2000 digital intermediate frequency system is introduced in this paper. The characteristics of AD9516 and the hardware circuit diagram of digital intermediate frequency system are presented in detail. We introduced the specific applications of this clock synthesis method in digital intermediate frequency system, described a new data communication pattern between MCU and AD9516, and offered the main registers’ configuration content of this chip. We also analyzed how to calculate clock jitter and phase noise of sampling clock. After the PCB board of this digital intermediate frequency be made, we debugged carefully to all parts of the PCB. At last, we tested the sampling clock’s clock jitter and phase noise. We also tested the SNR of the whole system. The quality of sampling clock satisfied the system requirements well. |
| Key words: digital intermediate frequency AD9516 phase noise clock jitter SNR |